1. Field of the Invention
The present invention relates to an input circuit, and more particular to an input circuit used for receiving signals exchanged among different semiconductor integrated circuits.
2. Description of the Prior Art
In general, this type of input circuit is used in transferring signals through bus lines or transmission cables interconnecting different integrated circuits. The input circuit receives signals and propagates the signal information to its own semiconductor integrated circuit. Therefore, without exception, every input circuit has a data input terminal for receiving signals from other integrated circuits and a data output terminal for propagating signal information to its own integrated circuit.
In recent years, as data transfer rate has been increased, it has come to be general that signals transferred among integrated circuits are low-amplitude signals on the order of 100 mV to 400 mV in spite that the power-source voltage of each integrated circuit is in the range of the order of 2 V to 5 V. Furthermore, in order to improve the reliability of logic signals, the differential-signal transmission system has come to be used instead of the single-ended signal transmission system that was the main system used formally. The differential-signal transmission system recognizes the difference of the amplitudes of two single-ended signals that are transferred simultaneously, thereby improving noise margins and reducing electromagnetic interference, and it is frequently used where fast and high-reliability processing is required.
Therefore, to support this type of transmission system, input circuits must provide functions of receiving differential signals and amplifying the voltages of low-amplitude data signals to voltages equal to or near the power-source voltages of their own integrated circuits.
Clock-triggered data processing methods, in which clock signals are used as triggers, are widely employed in integrated circuits to avoid loss of information due to data signal conflicts or time-varying factors in performing operations on the information propagated from the input circuits. A flip-flop circuit is known as a typical circuit of the clock-triggered type, which receives clock and data signals and temporarily stores the data in response to the transition timing of the clock signal.
FIG. 4 shows an exemplary data processing operation when the prior-art input circuit is connected to a flip-flop circuit.
Referring to FIG. 4, reference numeral 49 indicates an input circuit, and reference numeral 50 indicates a flip-flop circuit. Input data signal DIN input to the input circuit 49 is a low-amplitude signal, and data signal DOUT output from the input circuit 49 is generally a signal with an amplitude equal to the power-source voltage. The output terminal of the input circuit 49 is connected to the data input terminal D of the flip-flop circuit 50. The flip-flop circuit 50 is equipped with a clock terminal (CK), the data input terminal (D), and a data output terminal (Q). The clock terminal CK receives a clock signal CK, and the data input terminal receives a data signal DOUT.
In FIG. 4, the input circuit 49 amplifies the input data signal DIN from its low amplitude to an amplitude near the amplitude (on the order of 2 V to 5 V) of the power-source voltage of the integrated circuit, and provides the amplified input data signal to the data input terminal (D) of the flip-flop circuit 50, which is an internal circuit. As shown in FIG. 5, the flip-flop circuit 50 latches the data signal DOUT in response to the rising transition of the clock signal CK, stores it temporarily, and outputs an output signal Q, also in response to the clock transition. At this time, the relative timing relationship between the clock signal CK and data signal DOUT for enabling normal operations of the flip-flop circuit 50 must satisfy a minimum setup time requirement Tsu and hold time requirement Th, so the phase of the clock signal CK is adjusted to satisfy these requirements.
The example of prior art shown in FIG. 4, however, presents two major problems. One of the problems is that the signal amplitude amplification operation of the input circuit 49 lacks speed, so it cannot support fast transmission rates, such as rates of several gigabits per second (Gbps). The other problem is that the input circuit 49 and the flip-flop circuit 50 are configured separately, so it is impossible to keep the delay time of the data signal DOUT of the input circuit 49 constant with respect to the clock signal CK in the process of supplying the output signal DOUT to the flip-flop circuit 50, making it difficult to keep the setup time Tsu and hold time Th within the range enabling normal operations of the flip-flop circuit 50.
FIG. 6 shows a prior-art input circuit that has been devised to solve these problems.
Referring to FIG. 6, reference numerals 1 to 4 indicate PMOS transistors, and reference numerals 5 to 11 indicate NMOS transistors. The source of the PMOS transistor 1 is connected to the power source (VDD), and the drain of the PMOS transistor 1 is connected to the drain of the NMOS transistor 5. Given that the source of the NMOS transistor 5 is kept at the ground potential, the PMOS transistor 1 and NMOS transistor 5 form a CMOS inverter having a noninverting output terminal Z and an inverting output terminal ZB as its input and output nodes, respectively. On the other hand, given that the source of the NMOS transistor 6 is kept at the ground potential, the PMOS transistor 2 and the NMOS transistor 5 form a CMOS inverter having an inverting output terminal ZB and a noninverting output terminal Z as its input and output nodes. This cross-couples the input and output nodes of the CMOS inverter consisting of the PMOS transistor 1 and NMOS transistor 5 with the input and output nodes of an CMOS inverter consisting of the PMOS transistor 2 and NMOS transistor 6, thereby forming a flip-flop circuit.
The source of a PMOS transistor 3 is connected to the power source (VDD); its drain is connected in common to the gates of both the PMOS transistor 1 and NMOS transistor 5; and its gate receives a clock signal CK1. The gates of the PMOS transistor 1 and NMOS transistor 5 and the drain of the PMOS transistor 3 are connected to the noninverting output terminal Z. The source of the PMOS transistor 4 is connected to the power source (VDD); its drain is connected in common to the gates of the PMOS transistor 2 and NMOS transistor 6; and its gate receives a clock signal CK1. The gates of both the PMOS transistor 2 and NMOS transistor 6 and the drain of the PMOS transistor 4 are connected to the inverting output terminal ZB.
The drains of the NMOS transistors 7 and 8 are connected to the sources of the NMOS transistors 5 and 6 mentioned above, respectively, and the sources of the NMOS transistors 7 and 8 are connected to ground (GND) through the NMOS transistor 9. The gates of the NMOS transistors 7 and 8 are connected to the noninverting data terminal D and inverting data terminal DB, respectively, and the gate of the NMOS transistor 9 receives a clock signal CK1. The drain of the NMOS transistor 10 is connected to the source of the NMOS transistor 5 and the drain of the NMOS transistor 7, and its source is connected to ground (GND). In contrast, the drain of the NMOS transistor 11 is connected to the source of the NMOS transistor 6 and the drain of the NMOS transistor 8, and the source of the NMOS transistor 11 is connected to ground (GND). The gates of NMOS transistors 10 and 11 receive a clock signal CK2.
Next, the operation of the flip-flop circuit shown in FIG. 6 will be described.
Referring to the timing diagram shown in FIG. 7, at time t=0, clock signal CK1 is at the low logic level while the noninverting output terminal Z and inverting output terminal ZB are at the high logic level. Next, when clock signal CK1 changes from low to high at time t=1, the input circuit temporarily retains the data signal D0 received at the noninverting data terminal D and outputs the data signal D0 from the noninverting output terminal Z. Subsequently, when the clock signal CK1 changes from high to low at time t=2, the noninverting output terminal Z and inverting output terminal ZB output a high again. Subsequent operations after t=2 are similar to the operations mentioned above, as shown in FIG. 7. The state in which the low of a clock signal CK1 brings both the noninverting output terminal Z and inverting output terminal ZB high is called a reset state.
The sequence of input circuit operations above will now be described further in detail with reference to FIG. 7.
First, at time t=0, since clock signal CK1 is at the low logic level, the PMOS transistors 3 and 4 are in the conducting state, and the NMOS transistor 9 is in the nonconducting state. Therefore, the signals on both the noninverting output terminal Z and inverting output terminal ZB go high, and the potential at this time becomes the same as that of the power source (VDD), that is, the circuit is in the so-called reset state.
Next, when the clock signal CK1 changes from low to high at time t=1, the PMOS transistors 3 and 4 are switched to the nonconducting state, and the NMOS transistor 9 is switched to the conducting state. At this time, if a data signal D0 that appears at the noninverting data terminal D is high and a data signal D0B that appears at the inverting data terminal DB is low, the NMOS transistor 7 is in the conducting state and the NMOS transistor 8 is in the nonconducting state. Therefore, the source of the NMOS transistor 5 is clamped to a potential equal to the ground (GND) potential because the NMOS transistors 7 and 9 are in the conducting state. Accordingly, the NMOS transistor 5 is also in the conducting state, and the inverting output terminal ZB goes low. The potential at this time is the same as the ground (GND) potential. This also switches the PMOS transistor 2 to the conducting state, clamping the noninverting output terminal Z to high, or the power-source (VDD) potential level. In this case, since the operation was reset at time t=0, the logic level of the noninverting output terminal Z remains unchanged, or high.
Clock signal CK2 changes with a fixed delay with respect to clock signal CK1. The clock signal CK2 changes from low to high and the NMOS transistors 10 and 11 transit from the nonconducting state to the conducting state, thereby clamping the sources of the NMOS transistors 5 and 6 to the ground (GND) potential level. This enables faster nonconducting-to-conducting state transition of the NMOS transistor 5 and PMOS transistor 2, hence faster operation.
Furthermore, when the clock signal CK1 changes from high to low at time t=2, the PMOS transistors 3 and 4 are switched again to the conducting state and the NMOS transistor 9 is switched to the nonconducting state. Therefore, both signals that appear on the noninverting output terminal Z and inverting output terminal ZB go high. A potential at this time is the same as the power-source (VDD) potential, and the operation returns to the reset state. Similar operations continue after time t=2, although when the clock signal CK1 changes from low to high, the conducting and nonconducting states of respective pairs of the PMOS transistors 1 and 2, the NMOS transistors 5 and 6, and the NMOS transistors 7 and 8 may be reversed depending on the variations in the logic of the signals received at the noninverting data terminal D and inverting data terminal DB.
For example, at time t=3, when the clock signal CK1 changes from low to high again, a data signal D1 received at the noninverting data terminal D is low, and a data signal D1B received at the inverting data terminal DB is high, the NMOS transistor 8 is accordingly in the conducting state and the NMOS transistor 7 is in the nonconducting state in contrast to the case of t=1. Therefore, the source of the NMOS transistor 6 is clamped to the ground (GND) potential because the NMOS transistors 8 and 9 are in the conducting state. This also switches the NMOS transistor 6 to the conducting state, and a signal that appears at the noninverting output terminal Z also goes low. At the same time, the PMOS transistor 3 is also switched to the conducting state, clamping the inverting output terminal ZB to high, or the power-source (VDD) potential level. In this case, since the reset state was retained at t=2, the logic of the signal appearing at the inverting output terminal ZB remains unchanged, or high.
The conventional latch-type input circuit shown in FIG. 6, however, presents a problem in that, especially when clock signals CK1 and CK2 change from high to low and signals at the noninverting output terminal Z and inverting output terminal ZB go high, or in the reset state, the amount of current flowing from the power source (VDD) is large, requiring large switching power. The reason for this will be described with reference to FIG. 7.
Referring to FIG. 6, the state transition from time t=1 to time t=2 described above will be taken as an example again. More specifically, it is assumed that, at time t=1, clock signal CK1 is at the high logic level, data signal D0 is at the high logic level, and data signal D0B is at the low logic level. At this time, the NMOS transistors 7, 6, and 9, the PMOS transistor 1, and the NMOS transistors 10 and 11 are in the conducting state, and the PMOS transistors 3, 4, and 2, and NMOS transistor 8 are in the nonconducting state.
This causes the noninverting output terminal Z to output a low, or a signal at the ground (GND) potential level, and the inverting output terminal ZB to output a high, or a signal at the power-source (VDD) potential level. At this time, since the NMOS transistor 6 is in the conducting state, the source and drain terminals of the NMOS transistor 6 and the drain terminal of NMOS transistor 8 are low, or at the ground (GND) potential level. When the clock signal CK2 changes from low to high, the NMOS transistors 10 and 11 are switched to the conducting state, thereby enabling faster nonconducting-to-conducting state transitions of the MOS transistors mentioned above.
Subsequently, while the clock signal CK1 changes from high to low at time t=2 and the clock signal CK2 changes from high to low at time t=2xe2x80x2 with a fixed delay with respect to the clock signal CK1, the PMOS transistors 3 and 4 are switched to the conducting state again, while the NMOS transistors 6 and 10 are in the conducting state, whereby a feedthrough current route from the power source (VDD) through the PMOS transistor 3, NMOS transistor 6, and NMOS transistor 11 to ground (GND) is formed. This causes feedthrough current to flow from the power source (VDD) to ground (GND), resulting in increased power consumption.
Furthermore, when the clock signal CK1 changes from high to low at time t=2 and the PMOS transistors 3 and 4 are switched to the conducting state again, the NMOS transistor 6 is switched to the conducting state. This causes the potentials of the source and drain terminals of the NMOS transistor 6 and the drain terminal of the NMOS transistor 8 to change from the ground (GND) potential to a potential near the power-source (VDD) potential. The source and drain of the NMOS transistor 6 have a large amount of parasitic capacitance, including diffusion layer capacitance of all the MOS transistors connected thereto and the capacitance of metal wiring interconnecting the MOS transistors. Therefore, a large amount of charge current for charging the parasitic capacitance flows from the power source (VDD) through the conducting elements of the PMOS transistor 3 and NMOS transistor 6, resulting in an increase in the switching power.
Object of the Invention
The object of the invention is to provide an input circuit capable of higher-speed operation with lower power consumption.
Summary of the Invention
An input circuit of the present invention has a data input means for the input of input data; a data latch means for latching the input data; a reset means for resetting the data latch means; a clock synchronization means for synchronizing the input of the input data to the data input means; and a latch enhancement means for blocking feedthrough current by functioning complementarily to the reset means and enhancing the latching operation of the data latch means.